Texas Instruments' ADC342x are a high-linearity, ultra-low power, quad-channel, 12-bit, 25 MSPS to 125 MSPS, ADC family. The devices are designed specifically to support demanding, high input frequency signals with large dynamic range requirements. An input clock divider allows more flexibility for system clock architecture design and the SYSREF input enables complete system synchronization. The ADC342x family supports serial low-voltage differential signaling (LVDS) in order to reduce the number of interface lines, thus allowing for high system integration density. The serial LVDS interface is two-wire, where each ADC data is serialized and output over two LVDS pairs. An internal phase-locked loop (PLL) multiplies the incoming ADC sampling clock to derive the bit clock that is used to serialize the 12-bit output data from each channel. In addition to the serial data streams, the frame and bit clocks are also transmitted as LVDS outputs.
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- Quad-channel
- 12-bit resolution
- Single supply: 1.8 V
- Serial LVDS interface
- Flexible input clock buffer with divide-by-1, -2, and -4
- SNR = 70.2 dBFS, SFDR = 87 dBc at fIN = 70 MHz
- Channel isolation: 105 dB
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- Ultra-low power consumption:
- Internal dither and chopper
- Support for multi-chip synchronization
- Pin-to-pin compatible with 14-bit version
- Package: VQFN-56 (8 mm x 8 mm)
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Texas Instruments' ADC342x are a high-linearity, ultra-low power, quad-channel, 12-bit, 25 MSPS to 125 MSPS, ADC family. The devices are designed specifically to support demanding, high input frequency signals with large dynamic range requirements. An input clock divider allows more flexibility for system clock architecture design and the SYSREF input enables complete system synchronization. The ADC342x family supports serial low-voltage differential signaling (LVDS) in order to reduce the number of interface lines, thus allowing for high system integration density. The serial LVDS interface is two-wire, where each ADC data is serialized and output over two LVDS pairs. An internal phase-locked loop (PLL) multiplies the incoming ADC sampling clock to derive the bit clock that is used to serialize the 12-bit output data from each channel. In addition to the serial data streams, the frame and bit clocks are also transmitted as LVDS outputs.
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