AD9234-1000 12-Bit 1 GSPS Dual ADC

ADI's dual ADC cores feature a multistage, differential pipelined architecture with integrated output error correction logic. Each ADC features wide-bandwidth buffered inputs supporting a variety of user-selectable input ranges. An integrated voltage reference eases design considerations. Each ADC data output is internally connected to an optional decimate-by-2 block.

The AD9234 has several functions that simplify the automatic gain control (AGC) function in a communications receiver. The programmable threshold detector allows monitoring of the incoming signal power using the fast detect output bits of the ADC. If the input signal level exceeds the programmable threshold, the fast detect indicator goes high. Because this threshold indicator has low-latency, the user can quickly turn down the system gain to avoid an overrange condition at the ADC input. In addition to the fast detect outputs, the AD9234 also offers signal monitoring capability. The signal monitoring block provides additional information about the signal being digitized by the ADC.

Key Value Props

• 1.5 W total power per channel at 1 GSPS
• Wide-full power bandwidth supports IF sampling of signals up to 2 GHz
• JESD204B (Subclass 1) coded serial digital outputs